When I simulate my counter in Modelsim, the outputs are undefined

Question

I've made counter in Quartus as schematic file. Then generated Verilog design file from that scheme. I was able to configure and run simulation in Modelsim, but outputs of counter (Q0..Q3) always stays in undefined state. I am very new to Verilog and FPGA, but i think in that scheme at least Q0 should change every clock cycle.

Here is generated code:

module jk_counter_full(
    clk,
    JKFF0,
    Q0,
    Q1,
    Q2,
    Q3,
    next
);

input wire  clk;
input wire  JKFF0;
output wire Q0;
output wire Q1;
output wire Q2;
output wire Q3;
output wire next;

reg in1;
wire    in2;
wire    in3;
wire    SYNTHESIZED_WIRE_8;
reg JKFF_inst2;
reg JKFF_inst4;
reg JKFF_inst6;

assign  Q1 = JKFF_inst2;
assign  Q2 = JKFF_inst4;
assign  Q3 = JKFF_inst6;
assign  SYNTHESIZED_WIRE_8 = 1;

always@(posedge clk)
begin
    in1 <= ~in1 & JKFF0 | in1 & ~JKFF0;
end

assign  in2 = in1 & JKFF_inst2;


always@(posedge clk)
begin
    JKFF_inst2 <= ~JKFF_inst2 & in1 | JKFF_inst2 & ~in1;
end

always@(posedge clk)
begin
    JKFF_inst4 <= ~JKFF_inst4 & in2 | JKFF_inst4 & ~in2;
end

assign  in3 = in2 & JKFF_inst4;

always@(posedge clk)
begin
    JKFF_inst6 <= ~JKFF_inst6 & in3 | JKFF_inst6 & ~in3;
end

assign  next = in3 & JKFF_inst6;

assign  Q0 = in1;

endmodule

In testbench i've set input of first trigger JKFF0 to 1, and set clk signal with 10 ns period.

timescale 1 ps/ 1 ps
module jk_counter_full_vlg_tst();
reg JKFF0;
reg clk;                                              
wire Q0;
wire Q1;
wire Q2;
wire Q3;
wire next;                         

jk_counter_full i1 (  
    .JKFF0(JKFF0),
    .Q0(Q0),
    .Q1(Q1),
    .Q2(Q2),
    .Q3(Q3),
    .clk(clk),
    .next(next)
);

initial                                                
begin                                                                           
clk = 0;
JKFF0 = 1;                                                                   
end
                                                   
always
#1000  clk =  ! clk;                                                 
                                                   
endmodule

Answer 1

Your outputs are unknown (x) because you did not initialize some of your signals.

For example, you declared in1 as a reg type. The default value for reg is x. This means in1 is x at the start of simulation (time 0). It stays x throughout the simulation since your assignment statement has unknowns on the RHS.

One way to fix that issue for simulation is to initialize in1:

reg in1 = 0;

This gets rid of the x on Q0.

The same is true for JKFF_inst2, etc.

Another way is to add a reset input signal to your module.

If you don't want to change the design, you can also initialize the signals from the testbench.