I wanted to figure out how many number of continuous assignment held in one wire/reg is legal based on SV LRM.
I looked over verilog and SV LRM and it states the below.
"Continuous assignments shall drive values onto nets or variables" - SV LRM 10.3
This means continous assignment on reg is allowed unlike verilog.
(Continuous assignments shall drive values onto nets - verilog LRM 6.1)
"The continuous assignment statement shall place a continuous assignment on a net or variable data type." - SV LRM 10.3.2
This means number of continuous assignment on wire/reg is limited to 1.
Compromising above two,
I concluded wire and reg can have only one continuous assignment for each in SV.
Then I wanted to check through compilation in Modelsim.
> testing multi assignments in reg
module test_1;
reg a;
assign a = 1;
assign a = 0;
endmodule
Console: " 'a' is driven by more than one continuous assignment "
So, this compilation seeked out multidriving on reg very well. Nothing to complain.
>testing multi assignments on wire
module test_2;
wire a;
assign a = 1;
assign a = 0;
endmodule
Console: " Compile of SVtest.sv was successful "
I expected the result to give out error.
However, this compilation didn't sort out error of multi drivers on wire.
Which means UVA allows double drive on wire quite different than I expected.
Question abstract:
Is my interpretation of SV LRM(only one continuous assignment is permitted on a wire/reg) wrong? Or Is it just simulator not strictly reflecting SV LRM?
Moreover, is interpretation that I made earlier(In verilog, continuous assignment is permitted only once on wire but not allowed on reg) also wrong?(based on "Continuous assignments shall drive values onto nets - verilog LRM 6.1")
A net/wire can have multiple continuous assignments, but no procedural assignments. A variable can have multiple procedural assignments, OR a single continuous assignment. See https://blogs.sw.siemens.com/verificationhorizons/2013/05/03/wire-vs-reg/