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verilogsimulationsystem-verilog

Use environment variable in include file path

How to use an environment variable in the include file path in SystemVerilog?

I used:

`include "$VAR/abc.sv"`

but it says file can not be opened/found.

Also tried

`include "${VAR}/abc.sv"`

but I have the same issue. I am using the Cadence Xcelium simulator.

Solution

  • The `include compiler directive is used in the Verilog source code, and it is a feature of the IEEE Std 1800-2017 (refer to section 22.4). Since the standard does not mention support for environment variables, simulators do not need to implement such a feature.

    It is common practice to omit the path, and specify the path with a simulator-specific option:

    `include "abc.sv"

    Simulators may support using environment variables on the command line when specifying the include path:

    +incdir+${VAR}

    The solution is to read the documentation for your simulator to see how to specify include paths and whether it is possible to use environment variables, and if so, what syntax is used. I know Xcelium supports +incdir+ on the command line and in -f files.