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verilogsystem-verilog

Check all values in array using a loop


An array is called

logic [7:0] data_match[1:0];

This is assigned value in an always_comb block. The values can be one of the following:

localparam      MATCHE_PASS  = 2'b00; // match success
localparam      MATCHE_FAIL  = 2'b01; // match failed
localparam      MATCHE_NA    = 2'b10; // match not applicable

Now in an always_comb block, I assign value to this:

logic design_fault;

Now design_fault is 1'b1 if any value inside data_match is MATCHE_FAIL. Otherwise, it is 1'b0.


Solution

  • Using For Loop

    always_comb begin
        design_fault = '0;
        for (int i=0; i<8; i=i+1) begin
            design_fault = design_fault | data_match[i]==MATCHE_FAIL;     
        end
    end
    

    Using single statement

    Due to your encoding, you can also do it without a loop in a single statement:

    assign design_fault = |({8{MATCHE_FAIL}} & data_match);
    

    But I believe that you first need to change the definition of data_match to be:

    logic [7:0][1:0] data_match;
    

    You first concatenate 8 duplicates of MATCHE_FAIL value. The data_match vector should be constructed in the same manner - 8 match results concatenated.

    This is why you need to change the data_match definition (double check me in simulation).

    Then you do bitwise AND between the two. Since your encoding defines that bitwise AND between MATCHE_FAIL to MACTHE_NA will give "2'b00", and the same for MATCHE_FAIL to MATCHE_PASS, it's enough to check that this bitwise AND result has any bit different than 1'b0.

    Therefore, you OR all the bits of the result as the final step.