Does anybody know how this code differentiates from normal D FF code?

Question

I am working on the verification project and inspecting DUT, I found something unnatural to me. There are tons of code snippets like below.

always @ (posedge clk) begin
    if(rst)      
        q <= 0;   
    else if(q != d)     
        q <= d;
end

I think this code works perfectly equal to normal D flip-flop code which is:

always @ (posedge clk) begin
    if(rst)     
        q <= 0;   
    else     
        q <= d;
end

Can anybody tell me why the code is written like that? Is there any special meaning?

I asked several colleagues about this topic but I haven't got a satisfied answer.

Answer 1

As far as RTL synthesis is concerned, they are functionally equivalent.

However, there is a difference in simulation if q or d is unknown('x). q remains in the unknown state until there is an explicit reset. And if d goes unknown, q remains in its current state.

I highly doubt this was the intent of the original author of this code. More likely it was a misunderstanding of how a D-FF should be modeled.