Is assigning a value on a module input permitted? I thought this would not be the case. I made example codes and tested these through EDA Playground.
Both of these turned out to have errors.
But, why it is not permitted?
module test(
input a,b,c
);
a=1; b=0; c=1;
endmodule
module test(
input wire a,b,c
);
a=1; b=0; c=1;
endmodule
These are the codes I tested.
The line a=1; b=0; c=1; is illegal because assignment operations must be part of an assign statement or within procedural blocks such as always, initial, task, and function. Inline assignments when declaring the signal as it is allowed because it treated as an inferred assign for net types (e.g. wire) and initial for non-net types (ex reg and integer).
Generally you should not drive a modules inputs within its definition. Doing so often results in driver conflict. The inputs should be driving at a higher level.
SystemVerilog allows default values for inputs as defined in IEEE1800-2017 § 23.2.2.4 Default port values. If the default is not specfied, then the default is high impedance ('z). It will only use the default value if the input is not connected for the module instance.
module test(
input a=1'b2,b=2'b0,c=2'b1
);
endmodule
Be aware that the default port value feature may not be implemented by all simulators, synthesizers, or other EDA tools. You will need to run tests with your tools.