The RTL viewer in Quartus is omitting redundant gates

Question

I have written Verilog code for 2 back to back not gates. However, when I pull up the RTL in the RTL viewer, the back to back not gates are not shown; instead, a wire is shown.

I am using Intel Quartus Lite 22.1

RTL view:

My Code:

module notnot(clk, outp);
input clk;
output outp;
wire a1;
not #(20) n1(a1,clk);
not #(20) n2(outp,d);
endmodule

module ini(a,b);
input a;
output b;
notnot poe1(a,b);
endmodule

How do I see the correct RTL?

Answer 1

The posted code does not connect two not gates. The output of the first gate needs to be connected to the input of the second. Its not connected in the post.

Metacomment /* synthesis keep */ instructs the tools to not minimize the combinational logic driving the wire.
See synthesis keep

Here is the notnot module with the output of the first gate connected to the input of the 2nd, and the /* synthesis keep */ attribute added to the wire that makes the connection.

module notnot(clk, outp);
  input clk;
  output outp;
  
  wire a1 /* synthesis keep */;
  
  not #(20) n1(a1,clk);
  //   not #(20) n2(outp,d);
  not #(20) n2(outp,a1);
  
endmodule

Another way to preserve the combitational logic is to insert a register between the gates.

module ini(clk,a,b);
  input a;
  input clk;
  output b;
  
  notnot poe1(clk,a,b);
  
endmodule

module notnot(clk,a, outp);
  input clk;
  input a;
  output reg outp;
  
  reg a_reg;
  
  not #(20) n1(a1,a);
  
  always@(posedge clk)
    a_reg <= a;
  
  not #(20) n2(outp,a_reg);
  
endmodule

Synthesis generally does not remove registers.
Synthesis may combine the two gates.
If so, then bring the output of the first gate to the top level as an output, which should prevent it from being removed. If it has its own output, then removal in synthesis would change he design (this would be way outside the intent of optimization).

The behavior you are observing is not an error; synthesis & place & route are deseigned to reduce logic to save resources. Its is tricky to prevent the optimization of combinational logic by synthesis, the tricks vary among tools.