How to correct this error "Illegal reference to net q"?

Question

I am getting this error when I am compiling my file which Using Behaviour Modelling is designing a positive edge triggered T-Flip-Flop with asynchronous clear in Verilog code.

module t_flip_flop (input clk, input pr, input clr, input d, output q);
  reg q_next;

  always @ (posedge clk or negedge clr) begin
    if (clr == 0) q_next <= 1'b0;
    else if (pr == 1) q_next <= d;
    else if (clk == 1'b1) q <= q_next;
  end
endmodule

module t_flip_flop_testbench;
  reg clk, pr, clr, d;
  wire q;

  t_flip_flop tff (clk, pr, clr, d, q);

  initial begin
    clk = 0;
    pr = 0;
    clr = 0;
    d = 0;
    #10
    clk = 1;
    #10
    clk = 0;
    pr = 1;
    d = 1;
    #10
    clk = 1;
    #10
    clk = 0;
    pr = 0;
    d = 0;
    #10
    clk = 1;
    #10
    clr = 1;
    #10
    clr = 0;
    #10
    $finish;
  end
endmodule

Answer 1

In the t_flip_flop module, q is implicitly a "net" type. You need to explicitly declare q as a reg type since you are making a procedural assignment to it inside the always block.

Change:

module t_flip_flop (input clk, input pr, input clr, input d, output q);

to:

module t_flip_flop (input clk, input pr, input clr, input d, output reg q);

That change fixes the error.

---

Unrelated to your reported error, the following line is a little unusual:

else if (clk == 1'b1) q <= q_next;

You likely want to get rid of the clk condition. While it may simulate as you wish, it might be a problem if you want to synthesize it.