SystemVerilog - dynamic types in non-procedural context error

Question

I need to bypass programming a bunch of registers in different blocks, the basic infrastructure is something like shown below. This gives me two types of errors:

Dynamic type in non-procedural context
Illegal reference in force/proc assign

Both of these are for line:

force top.design0.register_block.in = in;

Is there any quick solution short of writing an FSM that goes over all register_values?

logic [31:0] register_values[2:0] = {'habcd, 'hbcde, 'hcdef };

class Injector;
    task automatic run();
        foreach (register_values[i])  force_reg(register_values[i]);
    endtask

    task automatic force_reg(input logic [31:0] in);
        @(negedge top.design0.register_block.clk);
        force top.design0.register_block.in = in;
        @(negedge top.design0.register_block.clk);
    endtask
endclass

module register_block(input  logic       clk,
                      input  logic[31:0] in);
endmodule

task force_registers();
    Injector injector = new();
    injector.run();
endtask

module design(input logic  clk);
    logic[31:0] in;
    register_block register_block(clk, in);
endmodule

module top();
    logic clk;
    design design0(clk);
    initial force_registers();
    initial begin
        clk = 0;
        forever #10 clk = ~clk;
    end
    initial #200 $finish;
endmodule

Tried the tasks without the 'automatic' but that gives same error.

Answer 1

Tasks defined in class are automatic by default. The tool complains about in which is a task argument. Since the task is automatic, the argument variable is considered to be automatic as well.

The way around it is to declare the task static:

task static force_reg(input logic [31:0] in);

Assuming, that there is only a single instance of the task 'run' at any time, it should work.