Why does Vivado not recognise packages without modules in System Verilog?

Question

I have a lengthy enum of opcodes that I want to include in a package so that it can be used in multiple locations throughout the project, this is:

typedef enum logic [6:2] {
  LOAD   = 5'b00_000,  LOAD_FP  = 5'b00_001,  CUSTOM_0   = 5'b00_010,  MISC_MEM = 5'b00_011,  OP_IMM = 5'b00_100,  AUIPC      = 5'b00_101,  OP_IMM_32 = 5'b00_110,  OP_48_1 = 5'b00_111,
//ect...
} base_opcode_map;

typedef enum logic [6:2] {
    R_TYPE  = { OP, OP_FP},
    R4_TYPE = { MADD, MSUB, NMSUB, NMADD},
    I_TYPE  = { LOAD, LOAD_FP, MISC_MEM, OP_IMM, OP_IMM_32 },
    S_TYPE  = { STORE, STORE_FP, AMO},
    B_TYPE  = { BRANCH, JALR},
    U_TYPE  = { AUIPC, LUI, OP_32},
    J_TYPE  = { JAL, SYSTEM }
} instruction_type;

This I want to include in multiple different modules E.G instruction decode and the ALU, however it appears Vivado does not recognise this or include it in the Design Sources as the file itself does not include any module of its own. I was hoping that there would be some neat solution for this?

I tried to include the package in the current top design source with:

import opcodes::base_opcode_map;

module instruction_decode(
    input [31:0] inst,
    output base_opcode_map [6:0] opcode,
    // others
    output reg [31:0] imm
    );
    assign opcode = base_opcode_map'(inst[6:2]);
    always @ * begin
        case (opcode)
            I_TYPE : begin
                imm[0] <= inst[20];
                imm[4:1] <= inst[24:21];
                imm[10:5] <= inst[30:25];
                imm[31:11] <= inst[31];
            end
// continued

However the compiler flags each of the conditional branches i.e I_TYPE : begin with an error saying [Synth 8-36] 'I_TYPE' is not declared ["C:/Users/lyndo/OneDrive/Documents/code/isa/risc_v/risc_v.srcs/sources_1/new/instruction_decode.sv":18] what should I do in this situation to get the IDE to recognise the file in the design sources?

Answer 1

Directly importing an enum typedef does import all of its associated names because an enum does not create an enclosing scope. You have to explicitly import each name along with the enum typedef, or you can use a wildcard import:

import opcodes::*;

Also, I'm not sure what you are trying to do with the enum instruction_type. You cannot nest enumeration encodings like that. There all need to be 5-bit encodings.