icarus verilog: Unable to bind variable

Question

I am trying to pass a string as parameter to a module and getting this error:

Unable to bind variable

module dut #(parameter string CONFIG_FILE) 
(
input logic clk
);
endmodule

module main;
localparam string CONFIG_FILE = "Config.txt";
logic clk;
                   
dut
# (.CONFIG_FILE (CONFIG_FILE)) 
dut_inst
(.clk(clk));

endmodule

Compile with icarus:

> iverilog -g2012 tb2.sv
------
tb2.sv:12: error: Unable to bind variable `CONFIG_FILE' in `main'
1 error(s) during elaboration.

Answer 1

I also got errors with iverilog on EDA Playground. The error message was different from yours, which likely means the version of iverilog is different.

This compiles without errors on EDA Playground

module dut #(parameter CONFIG_FILE="file.txt") 
(
input logic clk
);
endmodule

module main;
localparam CONFIG_FILE = "Config.txt";
logic clk;
                   
dut
# (.CONFIG_FILE (CONFIG_FILE)) 
dut_inst
(.clk(clk));

endmodule

That version does not like string being used with parameters, apparently. However, in this case, it is not necessary to use the string keyword.

It also required a default value for the parameter.

iverilog doesn't support all SystemVerilog features (IEEE Std 1800-2017).