How to make a constant binary number adapt to a Generic statement in VHDL

Question

As you can see, I am trying to make a generic component that tests if a number is equals to one (using WHEN ELSE for that).

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY isone IS
GENERIC ( N: integer );
PORT (a : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
      equals : OUT STD_LOGIC);
END isone;

ARCHITECTURE rtl OF isone IS
BEGIN
    equals <= '1' WHEN A = "0001" ELSE '0';
END rtl;

My problem is, how do I adapt the "0001" in equals <= '1' WHEN A = "0001" ELSE '0'; to extend its size when, for example, the Generic N value is 8?

Only solution that I thought of was changing the "0001" for a a-a +'1' (pretty bad one)

Answer 1

You can use the conversion functions of the standard package "numeric_std":

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY isone IS
    GENERIC ( N: integer );
    PORT (a : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0);
          equals : OUT STD_LOGIC);
END isone;

ARCHITECTURE rtl OF isone IS
    CONSTANT ONE : STD_LOGIC_VECTOR(N-1 DOWNTO 0) := STD_LOGIC_VECTOR(TO_UNSIGNED(1, N));
BEGIN
    equals <= '1' WHEN A = one ELSE '0';
END rtl;