Assigning the entirety of a 2D packed array to a 1D packed array with the same number of elements

Question

I have the following signals:

logic [X-1:0][Y-1:0] twoDim;
logic [(X*Y)-1:0]    oneDim;

I want to assign the entirety of twoDim to oneDim i.e. if I wrote something like this:

assign oneDim = twoDim;

And parameter X = 5 then I would expect the behaviour to be the same as the following:

assign oneDim = { twoDim[4], twoDim[3], twoDim[2], twoDim[1], twoDim[0] };

How would this be accomplished succintly in Synthesizable SystemVerilog for all possible values of X, Y (which are int unsigned) ?

Answer 1

For packed aggregate types, you do not need to go through all this trouble. The following will be sufficient. System verilog allows assigning arrays of compatible types (7.6).

   assign oneDim = twoDim;