Verilog delayed signal not toggling

Question

I have the following Code:

`timescale 1ps / 1ps 

module tb;
localparam  t_CLOCK_PERIOD          = 1000;
bit         clk;    
bit         clk_del;

always #(t_CLOCK_PERIOD/2)      clk         = ~clk;
assign #490                     clk_del     = clk;// clk_del toggling normally
//assign #510                   clk_del     = clk;// clk_del not toggling

initial begin
    clk =1'b1;
    $display("waiting for Clock delayed");
    @(posedge clk_del);
    $display("Clock delayed");
    $finish;
end
endmodule

I am trying to delay a clock signal, but when I do that by more of half a period, the signal stays unassigned (it does not toggle).

What am I doing wrong? How can I delay this signal more that the half period?

Answer 1

Your clk_del assign statement does not work with the 510 delay because the RHS (clk) changes more quickly than the delay. It is like you are always sampling clk when it is 0. The assign statement is confusing, and it is not the proper way to generate two related clock signals.

You can control the phase relationship between the 2 clocks by using an initial delay for the delayed clock. This approach is more conventional and is easier to understand:

always #(t_CLOCK_PERIOD/2) clk = ~clk;

initial begin
    clk_del = 1;
    #10;
    forever #(t_CLOCK_PERIOD/2) clk_del = ~clk_del;
end

By varying the initial value of clk_del and the initial delay value, you can achieve any phase relationship you want.