Conditional Assignment in Verilog

Question

I came across this code and was hoping someone could help me with it.

I understand that this means that out equals to out_1 if either a0, a1, a2, a3 is 1. If not, we have to look at the second expression which is 1'd0. Any idea what variable does the 1'd0 refer to? Or is this not allowed (I could compile it though).

out <= (a0 | a1 | a2 | a3) ? out_1 :
       ( 1'd0 )            ? out_2 :
       (a4 | a5 | a6 | a7) ? out_3 :
       out_4;

Answer 1

I think you are confused by this code because the code is a little odd.

You have a compound conditional assignment. There are 3 conditions: the expressions within parentheses.

You understand how the 1st condition works. That's great.

The 2nd condition works in a similar fashion: if the condition is true, then assign out to out_2. In this case, the condition is a constant, not a variable. Since the constant has the value 0, the condition will never be true, and out will never be assigned to out_2.

If the 1st and 2nd conditions are not true, the statement continues with the 3rd condition, etc.

This code can be simplified by removing the 2nd condition:

out <= (a0 | a1 | a2 | a3) ? out_1 :
       (a4 | a5 | a6 | a7) ? out_3 :
       out_4;

This code will simulate the same way as the code in the question.