Verilog NAND bit operation on 8-bit reg

Question

I'm writing a code in Verilog, and I have 2 inputs each one of those is 8-bit: A, B. I want to output

((notA) nand B)

but it seems like I can't do it in the same way as other operations where I do like and/or where I can just do

output = A|B , output = A&&B

I have tried to do

output = ~(~A&&B)

but it seems like it's not working properly.

Answer 1

Let's assume your output is also 8-bit. The likely problem with your code is that you are using the logical AND operator (&&) instead of the bitwise operator (&). The following code does a bitwise NOT of a, does a bitwise AND of that result with b, then does a bitwise NOT of the final result:

~( (~a) & b );

I added extra space for readability, and parentheses to leave no doubt about operator precedence.

Refer to IEEE Std 1800-2017, section 11.3 Operators.

This is a complete testbench for the code:

module tb;

logic [7:0] a, b, y;

assign y = ~( (~a) & b );

initial begin
    $monitorb(a,,b,,y);
    #5 a = 0      ;  b = 0;
    #5 a = '1     ;  b = '1;
    #5 a = '1     ;  b = '0;
    #5 a = 'h55   ;  b = 'haa;
    #5 a = 'h33   ;  b = 'hcc;
end

endmodule

Prints:

xxxxxxxx xxxxxxxx xxxxxxxx
00000000 00000000 11111111
11111111 11111111 11111111
11111111 00000000 11111111
01010101 10101010 01010101
00110011 11001100 00110011