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verilogsystem-verilogtest-bench

How do I continuously put data from full duplex dual port SRAM's port to port?


In a full duplex dual port SRAM, I'm trying to read data and write data from A port to B port without wait time.

    module tb_fbdp_ram();
    
        // Define our controlled signals
        reg clk=0;
        reg cs=0;
        reg a_we, a_oe, b_we=0, b_oe=1;
        wire [7:0] a_data;     // this is the connection to ramcu data port
        reg [7:0] a_addr=0;     // this is the address for port A
        wire [7:0] b_data;     // this is the connection to ramcu data port
        reg [7:0] b_addr=0;     // this is the address for port A
    
        reg  [7:0] a_data_value; // need a register to store value to send on a write
        reg  [7:0] b_data_value; // need a register to store value to send on a write
    
        // Instantiate our DUT
        fbdp_ram dut (
            clk     , // clock input
            cs      , // chip select
            a_we    , // channel A write enable
            a_oe    , // channel A output enable
            a_addr  , // channel A address
            a_data  , // channel A inout data
            b_we    , // channel B write enable
            b_oe    , // channel B output enable
            b_addr  , // channel B address
            b_data    // channel B inout data
    );
    
    assign a_data = !a_oe ? a_data_value : 'bz;
    assign b_data = !b_oe ? b_data_value : 'bz;
    
    
    always #5 clk = ~clk;
    
    
    initial begin


    for(int i=0; i< 15; i++) begin
    @(posedge clk);
    // set up initial conditions
    cs      = 1;
    a_we    = 1;
    a_oe    = 0;
    a_addr  = i;
    a_data_value = $urandom%10;
    end
    // set up initial conditions
    for(int i=0; i< 15; i++) begin
    @(posedge clk);
    cs      = 1;
    a_we    = 0;
    a_oe    = 1;
    a_addr  = i;

    b_we    = 1;
    b_oe    = 0;
    b_addr  = i+20;
    b_data_value = a_data;
    end
end

I read some data from A port and write them right away into the B port. But, the B port's input data from A port is delayed by one clock.

enter image description here

As you can see in the picture, 'h08 value is put into the B port's data, not 'h09. How can I write 'h09 not 'h08?


Solution

  • First remove the line b_data_value = a_data;

    Toward the end of your testbench, and outside of any other blocks, add:

    assign b_data_value = a_data;

    For example:

      // ...
      // ...
      // set up initial conditions
      for(int i=0; i< 15; i++) begin
        @(posedge clk);
        cs      = 1;
        a_we    = 0;
        a_oe    = 1;
        a_addr  = i;
    
        b_we    = 1;
        b_oe    = 0;
        b_addr  = i+20;
      end
      // combinatorially assign to ensure instantaneous writing to b_data
      assign b_data_value = a_data;
    end