Prevent Latch for Register File implementation

Question

I am design a register file module and I am trying to prevent the "inferred latch warning". The module allows for asynchronous reads but synchronous writes. This is what I have designed so far. I generally know what latches are, but can't think of a solution to prevent latches in this case. What would I define as the else statement so that the regfile doesn't create inferred latches?

module register_file (
    input wire clk,
    input wire rst,
    input wire [4:0] raddr_a,
    input wire [4:0] raddr_b,
    output reg [15:0] rdata_a,
    output reg [15:0] rdata_b,
    input wire [4:0] waddr,
    input wire [15:0] wdata,
    input wire we
);
    reg [15:0] regfile [0:31];
    /// 32 x 16 bit register file
    // asynchronous reads


    // don't allow read zero register
    assign rdata_a = (raddr_a == 5'd0) ? 16'd0 : regfile[raddr_a];
    assign rdata_b = (raddr_b == 5'd0) ? 16'd0 : regfile[raddr_b];

    integer i;
    always @(clk) begin
        // reset registers
        if (rst) begin
            for (i = 0; i < 32; i = i + 1) begin 
                regfile[i] <= 0;
            end 
        end else begin
            // if write enabled, write to register at waddr
            if (we == 1'b1) begin
                regfile[waddr] <= wdata;
            end
        end 
    end 
endmodule

Would I set the value to itself? How would I go on preventing an inferring latch? Thanks!

Answer 1

Change always statement from:

  always @(clk) begin

to:

  always @(posedge clk) begin

I was able to run the posted code on EDA Playground Yosys; it produces latches.
After the change, latches are no longer produced.