While searching for solutions related to the Verilog code error message 'range must be bounded by constant expressions", I came across answers that pointed to the SystemVerilog LRM's use of part-select addressing such as this earlier post.
I successfully applied such descriptions for most of my vector assignments.
There was, however, a description that the tool didn't like. I searched for an alternative and found that the expression [ lsb_base_expr +- width_expr ] could work. I tried it and it seems to be working. I want to find where the LRM describes it or if it is somehow something I should not use for synthesis purposes.
Sections 7.4.6 Indexing and slicing of arrays and 11.5.1 Vector bit-select and part-select addressing both describe this syntax.
This gets synthesized as a barrel shifter. The fact that you cannot have variable width operands is a language restriction, unrelated to synthesis.