I'm a SW developer trying to understand configuration of the RISC-V Platform-Level Interrupt Controller (PLIC) that's in a rocket-chip derived SoC in an FPGA. Please correct me if my terminology is off.
I'm trying to programmatically configure the PLIC after a warm boot, in particular clearing interrupt pending bits. I've read the RISC-V PLIC Specification which talks about up to 15872 contexts. While I can certainly iterate over all contexts with 1024 interrupts each, I would like to be more economical.
Where do I find the actual number of contexts? Is it constant for all rocket-chips designs? Is it a tunable value? What is the right question to ask the FPGA colleagues? They use chisel which I understand to be some sort of design language or tool.
To clarify terminology: What is a hart context?
We use the term hart to unambiguously and concisely describe a hardware thread as opposed to software-managed thread contexts.
The RISCV specification allows for up to 15872 contexts, but in practice you'll see many fewer - The actual number is set by each specific RISCV implementation. It is customizable in rocket-chip, so it could vary. The default configuration may offer more insight, but your specific configuration could be anything.
Your questions:
Where do the contexts come from? Where do I find the total number of contexts?
You can speculate what the number should be from implementation details, but as far as I'm aware there is no register that says how many contexts there might be. This will be implementation specific. Your best bet is looking at your rocket chip configuration.
From the Linux core docs:
A hart context is a privilege mode in a hardware execution thread. For example, in an 4 core system with 2-way SMT, you have 8 harts and probably at least two privilege modes per hart; machine mode and supervisor mode.
That means you would have 16 contexts for that case (4 cores x 2 threads x 2 privilege modes).
From this issue:
PLIC contexts are 1:1 with harts' interruptible privilege modes. (e.g. if you have 3 harts, each of which supports taking interrupts into M-mode and S-mode, you have 6 contexts.)
In this case, M mode and S mode are privilege modes.
Is there a Scala/Chisel/VHDL line of code to grep for the number of contexts?
No. The best you'll probably be able to do is find relevant values in your rocket-chip configs and figure out what it should be. Or ask someone with lots of RISCV experience on your team what the number should be. There isn't a register that stores the total number of contexts.
Is it constant for all rocket-chips designs?
No. The design could specify any number of harts or user modes. This is implementation specific and rocket-chip doesn't enforce any particular values.
Is it a tunable value?
Yes. The spec mentions a maximum, but in practice it can be any number <= that spec.
What is the right question to ask the FPGA colleagues?
Ask what is the maximum number of contexts they expect. If they don't know, ask them how many harts there are in your implementation, and how many user modes. Then multiply the two.
RISCV Wikipedia page
Official RISCV specification
RISCV PLIC specification
Rocket-chip docs
Chisel docs