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functiontaskverilogsystem-verilogforward-declaration

Forward declare a function/task


I browsed through the internet, and I've only saw people doing forward declarations on class using the typedef keyword. But, I was wondering how'd I do that with functions/tasks?

I wanted to put the main function above the definitions of other functions/tasks to ease the reader when one is previewing it. In C++, forward declaration for a function looks something like this:

//forward declaration of sub2
int sub2(int A, int B);

int main(){
    cout << "Difference: " << sub2(25, 10);
    return 0;
}

int sub2(int A, int B) //Defining sub2 here{
    return A - B;
}

For SystemVerilog, will it be something like this?

function somefunction();

virtual task body();
    somefunction();
endtask: body

function somefunction();
    // do something here.
endfunction: somefunction

Should I use typedef for forward declarations with functions/tasks?


Solution

  • Functions and tasks do not need to be declared before use as long as they have a set of trailing parenthesis () which may also include required arguments. They use search rules similar to hierarchical references. See section 23.8.1 Task and function name resolution in the IEEE 1800-2017 SystemVerilog LRM