How to design a decoder circuits with start position and fixed length?

I have a task but don't know how to implement it? I want to generate a fixed length output containing consecutive 1 output using combinatorial logic. This is an Example:

// input          input         output
// start_id(0~63) id_num(0~63)  id_mask
// 0              0             {64{0}}
// 0              2             {62{0},2{1}}
// 2              16            {46{0},16{1},2{0}}
// ...            ...           ...
// 60             16            60+16>64, ignore this situation

Solution

I'll give you an idea and a pseudocode.

Each of your ouputs have to be connected to a mux with two options: 0 or 1.
The select logic for the input must be driven by the input.

Regarding the logic:

Calculate start and end conditions.
AND both conditions to have a 1 at the output. This is what feeds the selector mux.

Pseudo code:

// 6 bits to represent 64 numbers
module(
    in  [5:0]  start_id,
    in  [5:0]  id_num,
    out [63:0] out_bitstring)

wire start_num[5:0];
wire   end_num[5:0];

assign start_num = start_id;
assign   end_num = start_id + id_num; // Need to do arithmetic properly!!

wire cond_a[63:0];
wire cond_b[63:0];

// HW for loop
for idx in range(64):

    cond_a[idx]         = (idx >= start_num);
    cond_b[idx]         = (idx <  end_num);
    out_bitstring[idx]  = ( cond_a & cond_b);

Some resources:

For loop in verilog