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verilogsystem-verilog

Is it possible to update variable location within loop in verilog/system verilog?

I am not sure about the term which is used to refer to the sizing of the variable. I will try to give as much details in the question as I can. I am working on a generalized implementation of a verilog code where, I want to update the pointer location that my code refers to in a for loop. For example: lets say I have a variable which can take in 8 bits values at a time

x[7:0] = some value;

I have a for loop which is initialized by an integer value, for e.g.

integer i;
for (i=large number; i>=1;i= i+1)
begin
  x = [(i*8)-1:i*(8-1)];
end

I am trying to make an assignment to x as shown in the code snippet above, but I get an error saying illegal operand for constant expression. Am I doing something fundamentally wrong or is there a way to achieve this?

Solution

  • Yes. Your code is illegal in (System)Verilog if i is a variable. Instead you need

    some_varaible = some_other_variable[index-:width];

    which is equivalent to

    some_varaible = {some_other_variable[index],some_other_variable[index-1],...,some_other_variable[index-width+1]};

    or

    some_varaible = some_other_variable[index+:width];

    which is equivalent to

    some_varaible = {some_other_variable[index+width-1],some_other_variable[index+width-2],...,some_other_variable[index]};