Passing bus array to another module via port mapping

Question

I have below code inside SV module where I instantiate another SV module and pass 5-bit bus to it to check for X and Z's as coded below:

  input  [4:0] analdo_trim; 
  cds_XZ_checker XZ_check_analdo_trim (.in(analdo_trim),.in_ok(analdo_trim_ok));

Here is module definition for cds_XZ_checker:

module cds_XZ_checker(in,in_ok);
input in;
output bit in_ok;

always_comb  begin              //Asynchronous assertion check block
      asynch_XZ_check: assert (!($isunknown(in))) in_ok=1'b1; 
        else begin 
            $warning ("WARNING (%M) digital signal in=%b is undefined at time %t",in,$time); 
            in_ok=1'b0;
        end//else
end

endmodule

The issue is when I read 5-bit analdo_trim in above module via in port, it only reads LSB of analdo_trim because it doesn't have bus width in declaration.

Module cds_XZ_checker is generic module which is instantiated inside several other modules. Hence, I can't declare 'in' as [4:0] as some other modules might pass bus with different bit width. Is there a way I can parameterize this so that it will work for any bit width?

Answer 1

You can use a parameter to accommodate different input bus widths:

module cds_XZ_checker #(parameter WIDTH=5) (in,in_ok);
input [WIDTH-1:0] in;
output bit in_ok;

always_comb  begin              //Asynchronous assertion check block
      asynch_XZ_check: assert (!($isunknown(in))) in_ok=1'b1; 
        else begin 
            $warning ("WARNING (%M) digital signal in=%b is undefined at time %t",in,$time); 
            in_ok=1'b0;
        end//else
end
endmodule

module tb;
    logic a,b;
    logic [4:0] c;
    logic d;

    cds_XZ_checker #(.WIDTH(1)) i0 (a, b);
    cds_XZ_checker i1 (c, d);
endmodule

The tb module shows how you would parameterize each instance of the checker module. The default width is 5. If your checker input is 5-bit, then passing the parameter is optional.

Demo on edaplayground