The following line of code val mod_subexp_array = Vec(9, Module(new SubTaylor(fepar)).io) produces the following error:
chisel3.package$ExpectedChiselTypeException: vec type 'AnonymousBundle(IO io in SubTaylor)' must be a Chisel type, not hardware
The module SubTaylor is a module I've written, and I interface with it via an IO port. My objective is to create 9 instances of these SubTaylor modules and chain them together using their IOs. To resolve the problem above, I thought perhaps the SubTaylor module needed to be wrapped within a Wire:
val mod_subexp_array = Vec(9, Wire(Module(new SubTaylor(fepar))).io)
However, the errors message changed to wire type 'AnonymousBundle(IO io in SubTaylor)' must be a Chisel type, not hardware. As I currently understand, there are two different Wire datatypes. One wire datatype is a Chisel type, and the other is a hardware type. Is my understanding correct? And how am I supposed to define Vector as a Chisel type?
What you want to write is the following:
val mod_subexp_array = VecInit(Seq.fill(9, Module(new SubTaylor(fepar))).io))
What that error message means is that you provided a hardware value instead of a type when a type was expected. I'll explain by analogy with C:
// This is how you make an Array of 10 ints
int my_array[10];
// This is analogous to Vec(9, Wire(Module(new SubTaylor(fepar))).io)
3 my_array[10]; /*
^ An int value instead of a type
*/
I know this distinction is a little more obvious in C than in Chisel (because Chisel is a generator metaprogramming framework), but it's effectively the same thing.
Vec(<n>, <type>) is how you create a Vec type. VecInit(<values>) is how you create a Vec value.
You may wonder why we are using Seq.fill? Seq is a Scala type and we are using a factory method to stamp out 9 instances of your Module. VecInit accepts a Seq of whatever hardware type you're creating so it will take those 9 instances and turn it into a hardware value.