EDAPlayground: Verilog code "reached maximum runtime"

Question

I have a simple Verilog code for a sequential logic network. It consists of a design and a testbench file; it compiles, but it runs for too long. I'm not sure why; apart from the clk, I didn't put any loops in it. Maybe I have some syntax mistakes using the binary numbers. I ran it using the online EDA Playground software; I didn't try it on Xilinx.

Simulator: Icarus Verilog 0.9.7, compile options: -Wall. "Execution interrupted or reached maximum runtime."

This is what the log wrote.

Design file:

module hazimodul(
  input clk,
  input rst,
  input ce,
  input x,
  output z
  
);
  

  reg[1:0] all;
  reg[3:0] y;
  reg[0:0] zout;
  
  always@(posedge clk)
  begin
    if(rst)
      begin
        zout <= 1'b0;
        all <= 2'b00;
        y <= 4'b0111;
      end
    else if(ce)
      begin
        if(all == 2'b00)
          begin
            if(x== 1'b0)
              zout<=1'b0;
            else 
              all <=2'b01;
          end
        if(all==2'b01)
          begin
            zout <= y[3:3];
            y <= {y[2:0],y[3:3]};
            if (y == 4'b0111)
              all <= 2'b10;
          end
        if(all==2'b10)
          begin
            if(x == 1'b0)
             all <= 2'b00;
             
          end
      end
  end
  
  assign z = zout;
  
endmodule 

Test file:

module test;

    reg clk;
    reg rst;
    reg x;
    reg ce;
  
  
    // Outputs
    wire z;

    // Instantiate the Unit Under Test (UUT)
    hazimodul uut (
        .clk(clk), 
        .rst(rst), 
      .x(x),
      .ce(ce),
      .z(z)
    );

    initial begin
        // Initialize Inputs
        clk = 0;
        rst = 0;
        x=0;
        ce=0;

        #10;
        rst<=1;
        #20;
        rst<=0;
        #30
        ce<=1;
        #40
        x<=1;
        #80
        x<=0;
        #90
        x<=1;
        
        
    end
    always #5
        clk <=~clk;
endmodule

Answer 1

You need to tell the simulator when to stop running. One way is to use the $finish system task, which you can add to your testbench:

initial #1000 $finish;

Now, the simulation finishes on edaplayground. You can change the #1000 delay to something more meaningful to your design.

---

Here is an explanation of why your code continues to run. Your testbench has 2 parallel threads: one initial block and one always block. In both threads, you add events to the Verilog event queue. The initial block ends after the last assignment to x.

However, the always block continues to add events to the event queue, so the simulation never ends.

Adding the second initial block with the $finish forces the simulation to end, regardless of the infinite always block.