Error: system call size not allowed in this dialect use system Verilog mode in Vivado

Question

I have a piece of Verilog code here

$size(data);

where data is a 16-bit number.

But, it gives an error in Vivado.

error: system call size not allowed in this dialect use system Verilog mode

I have tried searching for a solution, but no luck, hence posting it here.

Answer 1

The error message means that the $size system function can only be used if SystemVerilog features are enabled in Vivado. One way to do so is to give your files a .sv extension.