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veriloghdlalu

ALU NOOP case infers a latch: Is this OK?

I'm designing an ALU in Verilog with a combinational always block and cases for every opcode. In the case of NOOP, nothing should happen, so I'm just setting result = result. I understand why this infers a latch. My question is: is there a better way or is an inferred latch the correct decision in this case?

always@(Rdest, Rsrc, opcode, reset) begin
  case(opcode)
    ...
    default:
    NOOP: result = result; //  Infers a latch
  endcase
end
Solution

  • In this case, it should be simple to avoid the latch. You can set result to a constant value, such as 0. The logic that uses result probably ignores it when the ALU executes a NOOP anyway:

      case(opcode)
    ...
    ADD     : result = a + b;
    NOOP    : result = 0; // some known value  
    default : result = 0; // some known value 
  endcase

    It is good to avoid latches in many cases due to their timing issues. See also: Why are inferred latches bad?