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verilogquartus

I want to type conversion in Quartus2 Verilog

I want to type conversion in Quartus2 Verilog.......

integer to reg

ex)

integer a = 10;

reg[3:0] b;

$cast(b,a);

but $cast is not supported synthesis..

Solution

  • There is no need to explicitly cast between integral types; Verilog is loosely typed and defines implicit casts between many different types. You can just write:

    b = a;

    Explicit casts is a SystemVerilog feature having two different forms: static and dynamic.

    You use a static cast to a built-in or used defined type:

    typedef reg [3:0] uint4_t;

b = uint4_t'(a);

    And that would be acceptable for synthesis.

    The dynamic $cast operator is targeted for class variable assignments with inheritance. It would not expect synthesis tools to support this.