<Verilog> May I know why EQ=1, but the output no response?

Question

I am trying to build a Finite State Machine vending machine which consists of Datapath Unit and Control Unit. The attached links is the Control unit which consists the input of EQ(Equal), GT(Greater) and product. When product is "1" and either EQ or GT is "1", the output will be out=product. However, in my problem, the verilog code shows correct for GT but not EQ. It seem that the output cannot response to EQ when it is high.

My design of the state diagram. State Diagram

My Verilog code. Verilog code

The result. Result Waveform

module dispense(
  input [1:0] product,
  input GT, EQ, rst, clk,
  output [1:0] out,
  output reg done,
  output R
  );
  reg [1:0] ps,ns; //Present State and Next State
  assign R=EQ||GT;
  //State encoding
  parameter [1:0] S0=2'b00, S1=2'b01, S2=2'b10;
  //Verilog segment Next State logic and Output logic
  always @*
    begin
     //out=0;
     done=0;
     case(ps)
       S0: if(product>0) ns=S1; else ns=S0; 
        S1: if(R) ns=S2; else ns=S1;
        S2: begin  done=1; ns=S0; end
        endcase
      end
        //out=product;
    
    assign out = (done==1)?product:0;

    //State Register
    always@(posedge clk)
        if (!rst) ps=S0;
        else ps=ns;
endmodule

Answer 1

The answer is very simple. Add ps and ns to your simulation charts and you will understand why.

At the beginning of your simulation you are in state S0. When the product is bigger than 0 (first yellow mark) you go to state S1. Then you are waiting for EQ or GT, but EQ fall down one clock cycle ago so next GT arrive.

Set EQ and GT one clock cycle later.