Behavioral Modeling is not a valid l-value in testbench.test

Question

I am trying to use two binary inputs A and B to get the binary output which is the F just like the truth table below, but it keeps saying:

main.v:36: error: F3 is not a valid l-value in testbench.test
main.v:27:      : F3 is declared here as wire.

This is the truth table for my model.

A1 A0 B1 B0| F3 F2 F1 F0
0  0  0  0 | 0  0  0  0
0  0  0  1 | 0  0  0  0
0  0  1  0 | 0  0  0  0
0  0  1  1 | 0  0  0  0
0  1  0  0 | 0  0  0  0
0  1  0  1 | 0  0  0  1
0  1  1  0 | 0  0  1  0
0  1  1  1 | 0  0  1  1
1  0  0  0 | 0  0  0  0
1  0  0  1 | 0  0  1  0
1  0  1  0 | 0  1  0  0
1  0  1  1 | 0  1  1  0
1  1  0  0 | 0  0  0  0
1  1  0  1 | 0  0  1  1
1  1  1  0 | 0  1  1  0
1  1  1  1 | 1  0  0  1
  

My icarus Verilog code is here:

module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
input A1,A0,B1,B0;
output F3,F2,F1,F0;


always@(A1 or A0 or B1 or B0) 
begin 

if({A1,A0}*{B1,B0})

begin
{F3,F2,F1,F0}=4'b0001;
{F3,F2,F1,F0}=4'b0010;
{F3,F2,F1,F0}=4'b0011;
{F3,F2,F1,F0}=4'b0010;
{F3,F2,F1,F0}=4'b0100;
{F3,F2,F1,F0}=4'b0110;
{F3,F2,F1,F0}=4'b1001;
end

end

endmodule 

module testbench;
reg [1:0] A,B; // these are like switches
wire F3,F2,F1,F0; // like an LED

//test the verilog model
Multiply test(A[1],A[0],B[1],B[0],F3,F2,F1,F0);

//Generate inputs
initial
begin//like {

//display the response of the circuit
//for every input combination


$display("--------------------------------------------------------");
$display("Multiplication of Two 2-Binary Inputs equal to 4-bit binary output");
$display("--------------------------------------------------------");
$display("Time\tA\tB\tF3\tF2\tF1,\tF0");
$display("--------------------------------------------------------");
$monitor("%g\t%d\t%d\t%d\t%d\t%d",$time,A,B,F3,F2,F1,F0);
#15 $finish;
end
initial begin A = 0; B = 0; end

always #1 B[0] = ~B[0];
always #2 B[1] = ~B[1];
always #4 A[0] = ~A[0];
always #8 A[1] = ~A[1];
always #3

$display("--------------------------------------------------------");

endmodule

Answer 1

Since you make assignments to F3 within an always block, you must declare it as reg. The same is true for F2, F1, F0:

module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
input A1,A0,B1,B0;
output F3,F2,F1,F0;
reg F3,F2,F1,F0;

---

That fixes the compile error and allows your simulation to run. However, I don't think that Verilog code matches the truth table.

A common way to code a truth table is to use a case statement:

module Multiply(A1,A0,B1,B0,F3,F2,F1,F0);
   input A1,A0,B1,B0;
   output F3,F2,F1,F0;
   reg    F3,F2,F1,F0;

   always @* begin 
        case ({A1,A0,B1,B0})
            4'b0101          : {F3,F2,F1,F0}=4'b0001;
            4'b0110          : {F3,F2,F1,F0}=4'b0010;
            4'b0111          : {F3,F2,F1,F0}=4'b0011;
            4'b1001          : {F3,F2,F1,F0}=4'b0010;
            4'b1010          : {F3,F2,F1,F0}=4'b0100;
            4'b1011, 4'b1110 : {F3,F2,F1,F0}=4'b0110;
            4'b1111          : {F3,F2,F1,F0}=4'b1001;
            default          : {F3,F2,F1,F0}=4'b0000;
        endcase
    end
endmodule