constraint dependents in array of classes

Question

How can I constraint 2 variables in an array of classes, when there is a dependent between different items of the array?

class X;
  rand bit en;
  rand int idx;

  constraint cnst1{
     idx inside {[0:9]};
  }
endclass

class Y;
   rand X arr_x[100];

   constraint cnst2{
      ???
   }
endclass

I want to create cnst2 that will guarantee that:

1. each idx optional value (0-9) will be set for at least one of the arr_x[i].idx .
2. for all of the arr_x[i] that have the same value of idx, at least 1 will have en set to 1.

for example:

let's say that only the following have idx == 9:

arr_x[0].idx == 9;
arr_x[13].idx == 9;
arr_x[44].idx == 9;
arr_x[75].idx == 9;
arr_x[81].idx == 9;
arr_x[93].idx == 9;

need to guarantee that:

arr_x[0].en | arr_x[13].en | arr_x[44].en | arr_x[75].en | arr_x[81].en | arr_x[93].en == 1;

and so on for every idx value;

Answer 1

You want the or array reduction method. Also create a helper array so you can iterate from 0-9. This constraint reads: if at least one element has the value 0-9, then one of those elements has to have en set.

bit iterator[10];
constraint cnst2{
  foreach(iterator[i])
       arr_x.or(x) with (i ==x.idx) -> // needed if idx will not have every value 0-9
         arr_x.or(y) with (i == y.idx && y.en);
}

See sections 18.5.8.2 Array reduction iterative constraints and 7.12.3 Array reduction methods in the IEEE 1800-2017 SystemVerilog LRM.