I'm trying to return a word which is defined as:
subtype word is std_logic_vector(word_len - 1 downto 0);
By concatenating a whole bunch of other inputs from a record like so (this is inside a switch block):
return get_opc(ins.op) & std_logic_vector(ins.val) & "0000"; -- TODO Replace these with some sort of others construct
However, different opcodes have different sets of other inputs and so the amount that needs to be right-filled with zeroes changes. I'm not a huge fan of manually hardcoding trailing zeroes, it's a mess ad it won't play well if I resize my word.
My instinct was to try:
return get_opc(ins.op) & std_logic_vector(ins.val) & (others => '0');
But apparently you can't use others as an aggregate in this context.
I know I could create a buffer the size of a word, fill it with zeroes and then slot my different inputs into different slices but AFAIK, that would be extremely verbose, requiring me to specify the start and end point of each slice rather than just concatenating them on the left. This would soon get very messy.
Is there any easy way around this that keeps everything concise?
If you use VHDL-2008 (or VHDL-2019!), you can return an aggregate like this:
return (get_opc(ins.op), std_logic_vector(ins.val), others => '0');
This assumes that your return type is constrained. In other words, this is OK:
function F return word is
begin
return (get_opc(ins.op), std_logic_vector(ins.val), others => '0');
end function;
whereas if your return type is unconstrained like this, then it is not OK:
function F return std_logic_vector is