I originally had a 'params_list.v' file where multiple global constraints were listed
// params_list.v file
localparam
parameter1 = 18'h00AB,
parameter2 = 18'h00CD;
The parameters were used in a specific module as shown below
// design_main_ORIGINAL.v file
module my_module
`include "params_list.v"
assign reg1 = parameter1[4:0];
assign reg2 = parameter2[4:0];
endmodule
The original 'params_list.v' file got divided into multiple header files 'header1.vh', 'header2.vh',
The definition for one of the files is shown below
// header1.vh
`ifndef _header1_vh_
`define _header1_vh_
`define param1 18'h00AB
`define param2 18'h00CD
`endif
The header files are then included in the main design file (*.v) using the following lines
// design_main_NEW.v file
`include “header1.vh”
`include “header2.vh”
module module_xyz(
assign reg1 = param1[4:0];
assign reg2 = param2[4:0];
);
endmodule
When compile, the following error keeps showing up
** Error: (vlog-13069) C:/my_path/main_module.v(440): near "[": syntax error, unexpected '['.
Would appreciate it if you could please shed some light on what I might be missing.
If you want to select a part of a literal, you need to enclose it in a concatenation
assign reg1 = {`param1}[4:0];
assign reg2 = {`param2}[4:0];
This only works in SystemVerilog. But if reg1 and reg2 are already 5-bit variables, there's no need to do any of this. It will automatically be truncated.