Clock cycle and R-type command execution times

Question

How long will the clock cycle take in ns and how long will it take for the R-type command ADD $1, $2, $3 to execute, in a:

Single-cycle datapath

Multi-cycle datapath

Pipelined datapath

Answer 1

For a single cycle processor, the timing of a cycle and the timing of an instruction are the same value.  All the functions have to be able to occur in the same cycle, so add up the timings of all the functions, and that is both the minimum timing that a cycle can be and also the timing of an instruction.

For multi-cycle processor and pipelined processor, the timing of cycles and instructions are separate, as instructions are spread over multiple cycles.

For the pipelined processor, every function (stage) must have the same cycle time, because all the stages overlap.  So, the cycle time is the max among the individual stages.  Multiply that cycle time by the number of stages and that is the duration of an instruction.  (Also due to the stage overlap, every instruction goes through every stage.).

So, this gives the timing of one instruction going through the whole pipeline; however, because instruction execution overlaps, in the ideal situation, there is one instruction completed per cycle, despite going through 5 pipeline stages at one cycle each, so that gives another answer to the number of cycles for an add instruction.

Multi-cycle, is more complicated (compared with pipelined) because without overlap of the stages there is no real requirement that (1) all stages have the same duration, and (2) that every instruction executes all of the stages.

Regarding the former, the timing of each stage is potentially varied, as there is no reason to draw out any individual stage longer than necessary.  The way that would be done is to run a much faster clock and make the individual stages some multiple of that faster clock.  For example, using a 1ns clock, the first stage could take 3 cycles for 3ns of work, then 2, 2, 4 and 2, respectively.  That makes the first question awkward to answer, because it asks in terms of clock speed which would have to be 1ns in my example, but could also be 1/2 ns or 1/4 ns, as long as each stage uses as many cycles as it needs to result in that duration.

Regarding the latter, the Data Mem stage is irrelevant to an add instruction, so would most likely be skipped by the stage controlling unit.  In that situation the timing of an add instruction would be the sum of just the relevant stages.