I have this assembly code which is executed on a MIPS processor with 5 pipeline stages. The question was if xori will cause a data hazard reading the add result from $s0 3 instructions later. The answer is no because writing back stage happens in the first half clock cycle while decoding stage happens in the second half cycle in MIPS according to my professor.
Now my question is in which half cycle will the remaining stages be executed as in: Fetch, Execution and memory stages?
add $s0, $s1, $s2
sub $t0, $s0, $t1
and $t2, $t1, $s0
xori $t3, $s0, 12
There are different design possibilities about how WB and ID can overlap.
Let's note first that WB is very simple. There is nothing remaining to compute, as the data (which reg & what value) are ready at the very top of the clock cycle. Most other stages have real computations to perform at the beginning of the clock before producing a useful value.
One common design suggested by book authors is that each of these operations (reg write & reg read) is sufficiently quick that one can occur in 1st half and the other can occur in 2nd half. This however, suggests to make use of the negative clock edge to initiate the the reg read in ID while the rest of the design uses the positive clock edge for everything else, and this is not necessarily a good thing to do. (Some purists would also argue that this doubles/halves the reported clock frequency.)
Another approach is that the register file has an internal bypass so that any register being read (of the two possible register sources) in the same clock cycle as one being written can supply the written value. I think this is a sensible approach, and doesn't require 1/2 clock cycle explanation.
And yet another approach is that since the gates for reading and writing in the register file will be open on that same register at the same time, then the written value will eventually propagate to the reader by the end of the cycle, even if the reader sees the old value initially.
Both of the last two explanations eliminate the mention of half cycles.
in which half cycle will the remaining stages be executed as in: Fetch, Execution and memory stages?
All of these use the whole clock cycle.