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mips

MIPS architecture perform an instruction called swap


Multi-cycle datapath MIPS

Please take a look at the Figure above.

This question related to computer organization and design textbook. In the class we got like this question.

Given the typical MIPS architecture figure, perform a new instruction called swap. The new instruction is R-type and swap the contents of rt and rs. Add any necessary control signal or hardware that you may need. Show details.


Solution

  • See this picture first

    The solution to this question would require a two clock-cycle design. The issue is that the MIPS architecture given in the question has two Read ports but only one Write port, see fig. 4.19 in page 324 in the textbook (Computer Organization and Design The Hardware/Software Approach). For example:

    Swap  $t1, $t2
    

    Therefore, this instruction cannot be done in a single cycle. We can get t1 and t2 simultaneously out of the register memory, but we can only write one at a time (i.e. we can do this part in one cycle). Therefore, we can immediately put t1 in t2, but we need an additional structure (like an external register or memory block as I showed in the picture) that holds t2 until t2 is written in t1, but this would be done in a second clock cycle. See the attached pictures for more information. You also need to build some logic to control which register gets written first. For example, the operation of writing t2 in t1 could be triggered with an additional control signal called e.g. swap.