Unknown Module Error in Verilog, but module exists already

I'm doing a prelab for a digital logic class I'm in. We had to design an n-bit counter and a half adder, and then another module where you use the nbitcounter and the half adder together.

I'm having problems instantiating the counter in my new module. It says that nbitcounter doesn't exist, but I'm looking at it in my list of design files and I've already run a test on it, so I know it works. Could anyone help me get to the bottom of this?

module nBitCounter
    #(parameter N=4)
    (input wire clr ,
     input wire clk ,
     output reg [N-1:0] q
    );
    
 always @(posedge clk or posedge clr)
 begin
    if (clr == 1)
        q <= 0;
    else
        q <= q + 1;
  end
endmodule

module counter2adder(clk, clr, s, c_out);
//Port and wire declarations:
    input wire clk, clr;
    output wire s, c_out;
    wire [2:0] out;
 //Logic:
    nBitCounter #(.N(2)) 2count(
    .clk(clk),
    .clr(clr),
    .q(out)
    );   
    
endmodule

As you can see, counter2adder isn't finished, but I stopped because I saw this error. Another thing. The file for the counter is called n-bitCounter.v. I don't know if that changes things.

Solution

When I compile your 2 modules, I get a compile error on the instance name. Change:

nBitCounter #(.N(2)) 2count(

to:

nBitCounter #(.N(2)) count2 (

Instance names, like all identifiers in Verilog, must not begin with a number (2count).

I also get a warning on the bit width of out. Change it to:

wire [1:0] out;

It is a common practice to name the file the same as the module. The nBitCounter module should be in a file named nBitCounter.v, for example.

If you still have problems compiling the 2 modules, just add them both to the same file until you can get help from your instructor on Vivado tool usage.