VDHL error: converted type of object near text or symbol "UNSIGNED" must match std_logic_vector type of target object

Question

I'm getting this error when I try to compile some VHDL code: Error (10409): VHDL Type Conversion error at <line>: converted type of object near text or symbol "UNSIGNED" must match std_logic_vector type of target object.

I think I understand that this error is saying a is instantiated as std_logic_vector, but since I have added unsigned when I use a in the architecture, they are not the same type anymore so they cannot be properly converted. However, when I try to add unsigned in the entity declaration for SW or in the signal declaration, I get another error saying "unsigned" is never used. Can anyone help?

Here is my code:

library ieee;           
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity E is 
    port( SW:   in   std_logic_vector(9 downto 0); 
          LEDG: out      std_logic_vector(4 downto 0)   
            ); 
end entity E; 

architecture main of E is 
signal a, b, c: std_logic_vector; 

begin 

a <= unsigned(SW(4 downto 0));
b <= unsigned(SW(9 downto 7));
c <= ('0' & a) + ('0' & b);
 
// non-relevant code

end architecture main; 
            

Answer 1

VHDL is very strict about types, it won't convert one type into another one unless you explicitly tell it to.

So to fix your error, you simply have to convert the unsigned value back to an std_logic_vector, i.e.:

a <= std_logic_vector(unsigned(SW(4 downto 0)));
b <= std_logic_vector(unsigned(SW(9 downto 7)));

However, there's not really any reason to convert to unsigned and then convert back to std_logic_vector straight away. So you might as well just do:

a <= SW(4 downto 0);
b <= SW(9 downto 7);

However, in both cases you'll still get errors, because you didn't define the length of a, b and c. So you should fix those declarations:

signal a : std_logic_vector(4 downto 0);
signal b : std_logic_vector(2 downto 0);
signal c : std_logic_vector(? downto ?); -- Can't infer this from your code.