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functionfor-loopverilogsystem-verilogsynthesis

Synthesized for loop in always_ff block


I want to write the following code to be more readable and nicer looking.

always_ff @(posedge clk or negedge rst_n) 
    if(!rst_n)
        line_pipe <= 0;
    else 
        begin
            line_pipe[00] <= Func(inline);
            line_pipe[01] <= Func(line_pipe[00]);
            line_pipe[02] <= Func(line_pipe[01]);
            line_pipe[03] <= Func(line_pipe[02]);
            line_pipe[04] <= Func(line_pipe[03]);
            line_pipe[05] <= Func(line_pipe[04]);
            line_pipe[06] <= Func(line_pipe[05]);
            line_pipe[07] <= Func(line_pipe[06]);
            line_pipe[08] <= Func(line_pipe[07]);
            line_pipe[09] <= Func(line_pipe[08]);
            line_pipe[10] <= Func(line_pipe[09]);
            line_pipe[11] <= Func(line_pipe[10]);
            line_pipe[12] <= Func(line_pipe[11]);
            line_pipe[13] <= Func(line_pipe[12]);
            line_pipe[14] <= Func(line_pipe[13]);
            line_pipe[15] <= Func(line_pipe[14]);
        end

Can I rewrite this code with a for loop?


Solution

  • Assuming your current code synthesizes, this should synthesize as well. You can use a for loop for 15 of the 16 assignments:

    always_ff @(posedge clk or negedge rst_n) 
        if(!rst_n)
            line_pipe <= 0;
        else 
            begin
                line_pipe[00] <= Func(inline);
                for (int i=1; i<16; i++) begin
                    line_pipe[i] <= Func(line_pipe[i-1]);
                end
            end