Invalid module instantiation

Question

I am trying to take a floating point input and split it it into its sign, mantissa and exponent values. At lines 7 and 8, my compiler (I'm using Icarus Verilog) is giving the error:

Invalid module instantiation

even though I haven't instantiated any module here.

module test(Input, exp, sign, mant);
  input [31:0]Input;
  output [7:0]exp;
  output sign;
  output [22:0]mant;

  mant = Input[22:0];
  exp = Input[30:23];
  sign = Input[31];
endmodule

Answer 1

You need to use the assign keyword to make continuous assignments:

module test(Input, exp, sign, mant);
  input [31:0]Input;
  output [7:0]exp;
  output sign;
  output [22:0]mant;

  assign mant = Input[22:0];
  assign exp = Input[30:23];
  assign sign = Input[31];
endmodule