Is it possible to declare conditionnal signals in io bundle?

Question

Is it possible to declare signal only if a parameter is set in chisel module ?

Like it :

class GbWrite (val debug_simu: Boolean = true) extends Module {
  val io = IO(new Bundle {
//...
    /* debug */
    if(debug_simu){
      val countcol = Output(UInt(32.W))
    }
  })
//...
  if(debug_simu) {
    io.countcol := pixelCount
  }
//...
}

This code give me an error :

[info] compiling 1 Scala source to /media/stockage/projets/GbVga/chisel/target/scala-2.12/classes ...
[error] /media/stockage/projets/GbVga/chisel/src/main/scala/gbvga/gbwrite.scala:40:8: value countcol is not a member of chisel3.Bundle{val GBHsync: chisel3.Bool; val GBVsync: chisel3.Bool; val GBClk: chisel3.Bool; val GBData: chisel3.UInt; val Maddr: chisel3.UInt; val Mdata: chisel3.UInt; val Mwrite: chisel3.Bool}
[error]     io.countcol := pixelCount
[error]        ^
[error] one error found
[error] Compilation failed

Answer 1

It is possible but you need to use a slightly different syntax. See: How do I create an optional I/O?. The problem is the conditional val you are creating is inside the scope of the if and thus not visible farther down in the code.