Error: ordered port connections cannot be mixed with named port connections

Question

I tried to implement half adder in Verilog HDL. I successfully wrote out the design source file and I was stuck by an error while instantiating my module in the testbench. What caused the problem?

The design is here:

module half_adder(a,b,sum,carry);

 input a,b;
 output sum,carry;

 assign sum=a^b;
 assign carry=a&b;

endmodule

And the testbench is:

What's wrong with the instantiation syntax?

Answer 1

you have an extra "," after the .carry(c)

`include "half_adder.v"

module half_adder_tb;

    reg i0,i1;
    wire s,c;

    half_adder HAI (
        .a(i0),
        .b(i1),
        .sum(s),
        .carry(c)
    )

endmodule;