How to to use the val name of selected element in a chisel Vector in the generated Verilog

Question

I'm trying to keep the Val name of a signal in the generated Verilog. The Val is a dynamically selected element from a chisel Vector(Vec). Below is my test case code:

val myVec    = Reg(Vec(10,UInt(32.W)))
val selected = myVec(io.sel).suggestedName("selected")

I can see in the generated verilog the Mux that takes the selcted element from myVec. However, it has a random name _T something. suggestName() didn't help. I've also tried @chiselName without any improvement. The reason I want this signal to have a meaningful name is for debug purposes(functionally it is correct)

Answer 1

This is a known bug, sorry for the confusion/frustration. Glossing over some details, it's difficult for Chisel to tell the difference between a dynamic index as a right-hand value (reading) vs. left-hand value (writing) which makes it hard to name.

You can work around this by connecting the output of a dynamic index to a Wire:

val myVec    = Reg(Vec(10,UInt(32.W)))
val selected = WireInit(myVec(io.sel))

The Wire will be named via the normal mechanisms so @chiselName, suggestName or standard reflective naming will work.

Executable example using Chisel v3.3.2: https://scastie.scala-lang.org/UWYCtq37ReaVcRrNBxRlOA