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verilogsystem-verilogxilinxiverilog

How can I make each module instance read from a unique file?


In top.v, I generate X_MAX*Y_MAX instances of a pe module. In pe.v, I want to initialize a memory generated specifically for that instance. For example, at x=0,y=1: "pe_memory_x0_y0.dat". This is what my top-level module looks like:

genvar x, y;
    generate for (y = 0; y < Y_MAX; y = y + 1) begin : ys
        for (x = 0; x < X_MAX; x = x + 1) begin : xs
         pe #(
            .X_MAX(X_MAX),
            .Y_MAX(Y_MAX),
            .X(x),
            .Y(y)
            )
            pe_inst(
                .clk(clk),
                ...
            );

Inside pe.v, things like

$display("Loading pe memory at (%0d,%0d)", X, Y);

work in an initial block! But when I need to $readmem$,

$readmemb({"pe_memory_", X, "_y", Y, ".dat"}, n_bound_sel_memory);

does not work:

X has indefinite width

Specifying a width for X, a parameter whose values comes from a genvar, just throws more errors.

I'm targeting Xilinx FPGAs, and I'm trying to simulate my design with iverilog.


Solution

  • You can use $sformatf to construct a file name:

    $readmemb($sformatf("pe_memory_%0d_y%0d.dat", X, Y), n_bound_sel_memory);
    

    Refer to IEEE Std 1800-2017, section 21.3.3 Formatting data to a string