Verilog: More efficient way to use ternary operator

Question

I have written the following assign statement:

assign F = (BCD == 4'd1 | BCD == 4'd2 | BCD == 4'd3 | BCD == 4'd4 | BCD == 4'd5) ? 1'b1 : 1'b0;

where if the BCD input (4-bits) is 1-5, the function returns a 1 and otherwise returns a 0. This works perfectly how I intended, but I'm looking for a more efficient way to write the "OR" parts. Is there a more efficient way to write this?

Answer 1

There's no need for the ternary operator here. The result of each equality(==) is 1-bit, and you are doing a bit-wise OR (|). You probably should be using a logical OR (||) whose result is also 1-bit.

assign F = (BCD == 4'd1 || BCD == 4'd2 || BCD == 4'd3 || BCD == 4'd4 || BCD == 4'd5);

In SystemVerilog which most tools are supporting, you can use the inside operator

assign F = BCD inside {[1:5]}; //  contiguous range
assign F = BCD inside {[1:3],5, [7:10]}; //  noncontiguous values