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verilogsystem-verilog

Using Module Parameter in Continuous assignment


I'm trying to use generate on this parameterized module, but I keep getting the wrong output.

module constant_gen #( 
     parameter [4:0]round = 5'b00
   )
   (
     output [31:0] con
    );
        
    assign con = {round};//{round,5'b00000,round,2'b00,round,5'b00000,round} ^ 32'h6547a98b;    
endmodule
// Testbench
module constGen_tb;

    logic clk_i = 1;
    typedef logic [31:0] data_m [20:0];
    
    localparam period = 2;
    data_m const_table;

    //simulate the clock
    always 
    begin
      clk_i= 1; #period; clk_i= 0; #period;  // // 40ns period at each clock edge
    end
    
    genvar i;
    generate
        for (i=0; i < 20; i++) begin : con_gen
            constant_gen #(.RN(i)) dut (const_table[i]);
        end
    endgenerate   
    
    
    always @(negedge clk_i)
    begin
       
       for (integer i = 0; i <= 20; i = i + 1) begin
            $display("const: %h",const_table[i]);
       end       
       $finish;
   
    end   

endmodule

Output:

const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 
const: 00000000 

Edaplayground: playground code here


Solution

  • In your example the name of the parameter round is not the same as you use in instantiation: RN. This should work:

              constant_gen #(.round(p)) dut (const_table[i]);
    

    there is a warning in compilation which you should have pay attention to:

    # ELBREAD: Warning: ELBREAD_0097 testbench.sv (21): Parameter 'RN' not found in work.constant_gen instantiated in unit work.const_gen_tb.