Testbench clk not advancing

Question

All my testbench is trying to do is verify whether or not the LED signal went high, but on Modelsim when I try and simulate it, the clock doesn't even start, but it initializes to zero. I can also step through my design so I don't appear to have an infinite loop or anything like that. Is there anything obviously wrong here, especially with regards to clock initialization and generation?

`timescale 1ns/100ps
 
module fir_filter_tb();
 reg clk, reset_n;
 reg led;

top top_level (
    .clk(clk),
    .reset_n(reset_n),
    .led(led)
    );
    
    initial
     begin
     $display($time, " << Starting the Simulation >>");
     clk = 1'b0; // at time 0
     reset_n = 0; // reset is active
     led = 0; // output is low
     #10 reset_n = 1'b1; // at time 20 release reset
     end
    
    always #10 clk = ~clk;

    always
    begin
         if (led ==  1'b1) begin
             $write($time, "Filter Successful");
         end else begin
             $write($time, "bleh you suck");
         end
    end
endmodule : fir_filter_tb

Answer 1

The problem is with the always block with led in it. Since there is no timing control, it prevents time from advancing (time remains stuck at 0). It creates an infinite zero-time loop.

One way to fix it is to use:

always @*

This will only trigger the block when led changes.