Blocking assignments in always block verilog?

Question

now I know in Verilog, to make a sequential logic you would almost always have use the non-blocking assignment (<=) in an always block. But does this rule also apply to internal variables? If blocking assignments were to be used for internal variables in an always block would it make it comb or seq logic?

So, for example, I'm trying to code a sequential prescaler module. It's output will only be a positive pulse of one clk period duration. It'll have a parameter value that will be the prescaler (how many clock cycles to divide the clk) and a counter variable to keep track of it.

I have count's assignments to be blocking assignments but the output, q to be non-blocking. For simulation purposes, the code works; the output of q is just the way I want it to be. If I change the assignments to be non-blocking, the output of q only works correctly for the 1st cycle of the parameter length, and then stays 0 forever for some reason (this might be because of the way its coded but, I can't seem to think of another way to code it). So is the way the code is right now behaving as a combinational or sequential logic? And, is this an acceptable thing to do in the industry? And is this synthesizable?

```
module scan_rate2(q, clk, reset_bar);
//I/O's
input clk;
input reset_bar;
output reg q;

//internal constants/variables
parameter prescaler = 8;
integer count = prescaler;

always @(posedge clk) begin
  if(reset_bar == 0)
        q <= 1'b0;
  else begin
        if (count == 0) begin
            q <= 1'b1;
            count = prescaler;
        end
        else
            q <= 1'b0;
  end
  count = count - 1; 
end 
endmodule

```

Answer 1

You should follow the industry practice which tells you to use non-blocking assignments for all outputs of the sequential logic. The only exclusion are temporary vars which are used to help in evaluation of complex expressions in sequential logic, provided that they are used only in a single block.

In you case using 'blocking' for the 'counter' will cause mismatch in synthesis behavior. Synthesis will create flops for both q and count. However, in your case with blocking assignment the count will be decremented immediately after it is being assigned the prescaled value, whether after synthesis, it will happen next cycle only.

So, you need a non-blocking. BTW initializing 'count' within declaration might work in fpga synthesis, but does not work in schematic synthesis, so it is better to initialize it differently. Unless I misinterpreted your intent, it should look like the following.

integer count;
always @(posedge clk) begin
  if(reset_bar == 0) begin
        q <= 1'b0;
        counter <= prescaler - 1;
  end
  else begin
        if (count == 0) begin
            q <= 1'b1;
            count <= prescaler -1;
        end
        else begin
            q <= 1'b0;
            count <= count - 1;
       end
  end
end 

You do not need temp vars there, but you for the illustration it can be done as the following:

...
integer tmp;
always ...
       else begin
            q <= 1'b0;
            tmp = count - 1; // you should use blocking here
            count <= tmp; // but here you should still use NBA
       end