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verilogsystem-verilogmodelsim

How to fix vector assignment (vlog-13069) error


My variable declarations are like below:

output [6:0] dout_7seg_3, dout_7seg_2, dout_7seg_1, dout_7seg_0;    
wire   [6:0] dout_7seg [3:0];

and I tried to assign each dout_7seg_i to dout_7seg [i] by coding like below:

assign dout_7seg_3 = dout_7seg [6:0][3];

I got error results like this:

Error: (vlog-13069) "[": syntax error, unexpected '[', expecting ';' or ','.

I also tried to use a generate block:

genvar i;
generate for (i = 0; i<7; i = i+1) begin
    assign dout_7seg_3 = dout_7seg [i:0][3]; //I wanted to code like dout_7seg_i = dout_7seg [6:0][i]
    end
endgenerate

and also had the same

vlog-13069 error

Can you help me fix these errors?


Solution

  • Since you are assigning all 7 bits, there is no need to use the packed range ([6:0]). Simply use:

    assign dout_7seg_3 = dout_7seg[3];
    assign dout_7seg_2 = dout_7seg[2];
    assign dout_7seg_1 = dout_7seg[1];
    assign dout_7seg_0 = dout_7seg[0];